Reading guide

Today, if we want to select the most concerned and popular words among Chinese people, I think "integrated circuit" must be elected with a high vote! Due to the "neck sticking" incident, the integrated circuit has become the "sword of Damocles" hanging on the head of China. If it is not solved, it will be impossible to sleep safely. The enthusiasm of the people throughout the country is high, and the state has also taken a series of measures to respond positively: first, integrated circuit has finally become a first-class discipline, and the investment in the field of integrated circuit is increasing day by day. Major universities have successively established integrated circuit colleges, and Nanjing has specially established an integrated circuit University... Integrated circuit is a kind of electronic integration technology, so, To what extent has the current electronic integration technology developed? Advanced electronic integration technology can integrate more than 100 million transistors in less than 1 square millimeter of the size of sesame seeds. The number of transistors integrated on a chip the size of a fingernail can easily exceed 10 billion or more. At present, the total population of the earth is less than 8 billion. This original article makes a comprehensive analysis of "electronic integration technology". Readers can understand that there are seven integration modes: electronic integration (5 + 2) classification, 2D integration, 2D + integration, 2.5D integration, 3D integration, 4D integration, cavity integration and planar integration.
ELECTRONIC INTEGRATION TECHNOLOGY
Electronic integration (5 + 2) classification
Electronic integration technology is divided into three levels: on-chip integration, in package integration and PCB board level integration. Its representative technologies are SOC, SIP and PCB (also known as SOP or sob).
The integration on the chip is mainly 2D, and the transistors are integrated in the wafer plane in the form of tiles; Similarly, the integration on PCB is mainly 2D, and the electronic components are tiled on the surface of PCB. Therefore, both belong to 2D integration.
For the integration in the package, the situation is much more complex, and the industry has not formed a unified consensus on the classification of electronic integration, which is one of the reasons why I write this article.
When understanding integration, people usually judge by physical structure. Today, we propose two important criteria for the classification of electronic integration technology: 1. Physical structure and 2. Electrical connection (electrical interconnection).
Through these two criteria, we divide electronic integration into seven categories: 2D integration, 2D + integration, 2.5D integration, 3D integration, 4D integration, cavity integration and planar integration. Among them, the first five categories are located on the substrate, belonging to the category of assembly, and the last two categories are located within the substrate, belonging to the category of substrate manufacturing. Therefore, it is named (5 + 2) classification. Please refer to the following table:
2D integration
2D integration refers to the integration mode of installing all chips and passive components horizontally on the surface of the substrate.
Take the lower left corner of the upper surface of the substrate as the origin, the plane of the upper surface of the substrate is the XY plane, and the normal of the substrate is the Z axis to create the coordinate system.
Physical structure: all chips and passive components are installed on the substrate plane, the chips and passive components are in direct contact with the XY plane, and the wiring and vias on the substrate are located below the XY plane; Electrical connection: all need to pass through the substrate (except for a few bonding points directly connected through bonding wires).
Our most common 2D integration technology is applied to MCM, some SIP and PCB.
MCM (multi chip module) multi chip module is a complete component formed by high-density installation of multiple bare chips on the same substrate.
In the traditional packaging field, all packaging is device-oriented, serves the chip, plays the role of chip protection, scale amplification and electrical connection, and there is no concept of integration. With the rise of MCM, the concept of integration has emerged in packaging, so packaging has also undergone essential changes. MCM has shifted the concept of packaging from chip to module, component or system.
The process route of 2D integrated SIP is very similar to MCM. The main difference between 2D integrated SIP and MCM is that the scale of 2D integrated SIP is larger than MCM and can form an independent system. Firstly, organic substrate or high-density ceramic substrate is fabricated, and then packaging and testing are carried out on this basis.
2D integration diagram
In addition, fowlp based integration, such as info, although there is no substrate, can also be attributed to 2D integration.
2D + integration
2D + integration refers to the traditional chip stack integration connected by bonding wires. Some people may ask, isn't chip stacking 3D? Why should it be defined as 2D + integration?
It is mainly based on the following two reasons: 1) 3D integration refers to integration through 3D TSV to a large extent. In order to avoid conceptual confusion, we define this traditional chip stack as 2D + integration; 2) Although the physical structure is 3D, its electrical interconnection needs to be through the substrate, that is, first bonded to the substrate through the bonding wire, and then electrically interconnected on the substrate. This is the same as 2D integration. What is better than 2D integration is the stacking of structure, which can save packaging space. Therefore, it is called 2D + integration.
Physical structure: all chips and passive components are located above the XY plane, some chips do not directly contact the substrate, and the wiring and vias on the substrate are located below the XY plane; Electrical connection: all need to pass through the substrate (except for a few bonding points directly connected through bonding wires).
Several integrations shown in the figure below belong to 2D + integration.
2D + integration diagram
In addition, the integration mode of Pop (package on package) class can also be reduced to 2D + integration according to its physical structure and electrical connection.
2.5D integration
2.5D, as the name suggests, is a dimension between 2D and 3D. It usually refers to a dimension with both 2D characteristics and some 3D characteristics. In reality, 2.5D does not exist.
Physical structure: all chips and passive components are above the XY plane, at least some chips and passive components are installed on the interposer, there are wiring and vias of the interposer above the XY plane, and there are wiring and vias of the substrate below the XY plane. Electrical connection: the interposer can provide the electrical connection of the chip located on the interposer.
The key to 2.5D integration lies in the interposer of the intermediate layer. Generally, there are several situations: 1) whether the intermediate layer adopts silicon adapter plate, 2) whether the intermediate layer adopts TSV, and 3) whether other types of adapter plates are adopted; On the silicon adapter plate, we call the via passing through the intermediate layer TSV, and for the glass adapter plate, we call it TGV.
TSV integration in silicon interlayer is the most common 2.5D integration technology. Chips are usually connected with the interlayer through microbump. The silicon substrate as the interlayer is connected with the substrate through bump. The surface of the silicon substrate is wired through RDL, and TSV is used as the channel for electrical connection between the upper and lower surfaces of the silicon substrate. This 2.5D integration is suitable for the situation of large chip scale and high pin density, The chip is generally installed on the silicon substrate in the form of flipchip.
Schematic diagram of 2.5D integration with TSV
The 2.5D integrated structure without TSV in the silicon interlayer is generally shown in the figure below. A large bare chip is directly installed on the substrate. The chip can be connected to the substrate by bond wire or flip chip. Due to the large area above the large chip, multiple small bare chips can be installed, but the small chip cannot be directly connected to the substrate, Therefore, it is necessary to insert an interposer, install multiple bare chips above the interposer, and the interposer has RDL wiring, which can lead the signal of the chip to the edge of the interposer, and then connect it to the substrate through bond wire. This kind of intermediate layer usually does not need TSV, but only needs to be electrically interconnected through the wiring on the upper surface of the interposer, which is connected with the packaging substrate by bond wire.
Schematic diagram of 2.5D integration without TSV
Now, EDA tools have good support for 2.5D integration. The following figure shows the 2.5D integration design implemented in Mentor (Siemens EDA).
2.5D integrated design implemented in Siemens EDA
3D Integration
The main difference between 3D Integration and 2.5D integration is that 2.5D integration is wiring and punching on the intermediary layer interposer, while 3D integration is directly punching (TSV) and wiring (RDL) on the chip to electrically connect the upper and lower chips.
Physical structure: all chips and passive components are located above the XY plane, the chips are stacked together, there is a TSV passing through the chip above the XY plane, and there are wiring and vias of the substrate below the XY plane. Electrical connection: the chip is directly electrically connected through TSV and RDL.
3D integration is mostly applied in similar chip stacks. Multiple identical chips are stacked vertically and interconnected through TSV passing through the chip stack, as shown in the figure below. Similar chip integration is mostly used in memory integration, such as DRAM stack, flash stack, etc.
3D Integration diagram of similar chips
In the 3D Integration of different types of chips, two different chips are generally stacked vertically, electrically connected together through TSV and interconnected with the substrate below. Sometimes it is necessary to make RDL on the chip surface to connect the upper and lower TSVs.
3D Integration diagram of different types of chips
Now, EDA tools have good support for 3D integration. The figure below shows the 3D integration design implemented in Mentor (Siemens EDA).
3D integrated design implemented in Siemens EDA
4D integration
Previously, we introduced 2D, 2D +, 2.5D, 3D integration, and how to define 4D integration?
In the several integrations described above, the Z axis of all chips, interposers and substrates is vertical upward in the three-dimensional coordinate system, that is, all substrates and chips are installed in parallel. In 4D integration, this situation has changed.
When the XY planes of different substrates are not parallel, that is, the z-axis direction of different substrates is offset, we can define this kind of integration as 4D integration. Physical structure: multiple substrates are installed in a non parallel manner. Components are installed on each substrate, and the installation methods of components are diversified. Electrical connection: the substrates are connected by flexible circuit or welding, and the electrical connection of chips on the substrate is diversified.
4D integration diagram based on rigid flexible substrate
Schematic diagram of air tight ceramic 4D integration
The definition of 4D integration is mainly about the orientation and interconnection mode of multiple substrates. Therefore, 4D integration will also include 2D, 2D +, 2.5D and 3D integration modes.
Through 4D integration technology, we can solve the problems that cannot be solved by parallel three-dimensional stacking, provide more and more flexible chip installation space, solve the heat dissipation problem of high-power chips, and the most important air tightness problem in aerospace, military and other applications. Now, EDA tools also have good support for 4D integration, as shown in the figure below, which shows the 4D integration design implemented in Mentor (Siemens EDA).
4D integrated design implemented in Siemens EDA
4D integration technology improves the flexibility and diversity of integration. Looking forward to the future, 4D integration technology must occupy a place in the integration mode of SIP, and will become an important integration technology after 2D, 2D +, 2.5D and 3D integration technologies.
In the strict physical sense, based on the existing human cognition, all objects are three-dimensional, two-dimensional foil does not exist, and four-dimensional space needs to be verified. In order to distinguish different integration modes, we divide them into five integration modes: 2D, 2D +, 2.5D, 3D and 4D.
Cavity integration
Cavity cavity is a hole slot opened on the substrate, which usually does not pass through all layers. The cavity can be open or closed in the inner space. The cavity can be a single-stage cavity or a multi-stage cavity. The so-called multi-stage cavity is to dig a cavity inside a cavity and shrink it step by step, just like a sinking square in a city.
Schematic diagram of multistage cavity
Schematic diagram of embedded cavity
Through the cavity structure, the stability of the bonding wire can be improved, the air tightness of the ceramic package can be enhanced, and the components can be installed on both sides through the cavity structure.
The stability of bonding line is improved by cavity structure
Components are installed on both sides through the cavity structure
Planar integration
Planar integration technology, also known as planar embedding technology, is a technology that makes planar passive devices such as resistance, capacitance and inductance through special materials and prints them on the surface of the substrate or embedded between the layers of the substrate.
Through the combination of design and process, the passive components such as resistance, capacitance and inductance are made on the surface or inner layer of the substrate by etching or printing to replace the passive components to be welded on the substrate surface, so as to improve the layout space and wiring freedom of the active chip. The resistance, capacitance and inductance produced by this method are basically not high, It will not affect the thickness of the substrate.
Summary of 7 integration technologies
Through the following table, we summarize the electronic integration technologies, classify the seven integration technologies through the two indicators of physical structure and electrical connection, and view their typical structures through illustrations.
In the following figure, we have gathered seven integration technologies into one design to make them have a big reunion. On the surface of the substrate from left to right, there are five kinds of integration: 2D, 2D +, 2.5D, 3D and 4D, respectively. Inside the substrate, there are two kinds of integration: cavity and planar.
Today, we summarize seven electronic integration technologies from the two criteria of physical structure and electrical connection. When I wrote here, I suddenly found that seven is a magical number. The song of seven sons, seven sons of Jian'an, seven sages of bamboo forest, seven colors of Yunnan, seven colors of light, red, orange, yellow, green, blue and purple... In fact, "seven" is a quite "martial arts" number. There are seven weapons, seven swords, seven monsters in the south of the Yangtze River, and seven sons of Quanzhen... In addition, there are also famous "seven sons of national defense" in Contemporary Chinese colleges and universities, My alma mater is also among them.
Summary
1) The seven (5 + 2) integration technologies described in this article: the concepts of 2D + integration and 4D integration were first proposed by me, and have not yet become the consensus of the industry.
2) Cavity integration and planar integration are usually not classified together with other integrations in the industry. I pulled them together with the other five integration technologies.
3) Among the seven integration technologies, 2D, 2.5D and 3D are relatively mature terms, but different people also have different views on the distinction of details. For example, is 2.5D without TSV in interposer